;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
; (C) Copyright 2006 Marvell International Ltd.
; All Rights Reserved
;
;*********************************************************************************
;
;        COPYRIGHT (c) 2004-2005 Intel Corporation
;
;   The information in this file is furnished for informational use only,
;   is subject to change without notice, and should not be construed as
;   a commitment by Intel Corporation. Intel Corporation assumes no
;   responsibility or liability for any errors or inaccuracies that may appear
;   in this document or any software that may be provided in association with
;   this document.
;
;*********************************************************************************
;
;  FILENAME:       xlli_Littleton_defs.inc - Platform specific default
;                  values for Monahans/Littleton platform bring up.
;
; LAST MODIFIED:   22-Jan-2007
;
;******************************************************************************
;
;       platform GPIO pin settings (Monahans/Littleton)
;


xlli_GPSR0_value        EQU     0x00000000      ; Set registers
xlli_GPSR1_value        EQU     0x00000000
xlli_GPSR2_value        EQU     0x00000000
xlli_GPSR3_value        EQU     0x00000000

xlli_GPCR0_value        EQU     0xFFFFFFFF      ; Clear registers
xlli_GPCR1_value        EQU     0x7FFFFFFF
xlli_GPCR2_value        EQU     0xFFFFFA00      ;; keep LCD uncleared for IPL Splash screen on
xlli_GPCR3_value        EQU     0xFFFFFFFF

xlli_GPDR0_value        EQU     0x00010000      ; Direction Registers
xlli_GPDR1_value        EQU     0x00000000      ; FF_TXD bit only!
xlli_GPDR2_value        EQU     0x00000140	    ;; keep LCD uncleared for IPL Splash screen on
xlli_GPDR3_value        EQU     0x00000800


;
;       STATIC MEMORY CONTROLLER SETTINGS FOR Monahans/Littleton
;
xlli_MDREFR_value       EQU     0x00000023
xlli_MSC0_value         EQU     0x7FF07FFA
xlli_MSC1_value         EQU     0x7FFC7FF8
xlli_MECR_value         EQU     0x00000001
xlli_MCMEM0_value       EQU     0x0001C391
xlli_MCMEM1_value       EQU     0x0001C391
xlli_MCATT0_value       EQU     0x0001C391
xlli_MCATT1_value       EQU     0x0001C391
xlli_MCIO0_value        EQU     0x0001C391
xlli_MCIO1_value        EQU     0x0001C391
xlli_FLYCNFG_value      EQU     0x00010001
xlli_MDMRSLP_value      EQU     0x0000C008
xlli_SXCNFG_value       EQU     0x40044004      ; Default value at boot up

xlli_CSMSADRCFG_value   EQU     0x2             ; CS0 & CS! set for 256 Mb, One bus mode
xlli_CSADRCFG0_value    EQU     0x00020000      ; Chip select 0 configuration
xlli_CSADRCFG1_value    EQU     0x003E080B      ; Chip select 1 configuration
xlli_CSADRCFG2_value    EQU     0x0032091D      ; Chip select 2 configuration (sync reads)
xlli_CSADRCFG3_value    EQU     0x003E080B      ; Chip select 3 configuration

xlli_EMPI_MFPR_value    EQU     0x00000041      ; Set to alternate function #1

;
; SDRAM Settings
;
xlli_MDCNFG_value_16    EQU     0x8000072F      ; SDRAM Config Reg - 16 bit bus
xlli_EMPI_value         EQU     0xF4000000      ; Default value
xlli_MDCNFG_value_32    EQU     0x8000072B      ; SDRAM Config Reg - 32 bit bus
xlli_MDMRS_value        EQU     0x60000033      ; SDRAM Mode Reg Set Config Reg

xlli_RCOMP_RCRNG_value          EQU     0x2     ; Resistive compensation range
xlli_RCOMP_REI                  EQU     0xC65D4 ; 2.0 second rcomp updates

;
; MEMORY PHYSICAL BASE ADDRESS(S)
;

xlli_SRAM_PHYSICAL_BASE      EQU       (0X5C000000)  ; Physical base address for SRAM
xlli_SDRAM_PHYSICAL_BASE     EQU       (0x80000000)  ; Physical base address for SDRAM

;
; Misc constants
;

xlli_MemSize_1Mb        EQU     0x00100000

xlli_p_PageTable        EQU     0xA1FFC000    ; Base address for memory Page Table
xlli_s_PageTable        EQU     0x00004000    ; Page Table size (4K words - 16 Kb)

xlli_v_xbBOOTROM        EQU     0x00000000

xlli_stack_pointer      EQU     0x0             ; Stack pointer in use

      END
